/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_G9_PINMUX_REG $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:48:28 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  G9_PINMUX_REG_REG_CAM_MCLK0  0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK1  0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK2  0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK3  0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK4  0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK5  0x14
#define  G9_PINMUX_REG_REG_CAM_XLR0  0x18
#define  G9_PINMUX_REG_REG_CAM_XLR1  0x1c
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA  0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL  0x24
#define  G9_PINMUX_REG_REG_PKG_TYPE  0x28
#define  G9_PINMUX_REG_REG_SPK_EN  0x2c
#define  G9_PINMUX_REG_REG_AUX0  0x30
#define  G9_PINMUX_REG_REG_PWM0  0x34
#define  G9_PINMUX_REG_REG_PWM1  0x38
#define  G9_PINMUX_REG_REG_PWM2  0x3c
#define  G9_PINMUX_REG_REG_PWM3  0x40
#define  G9_PINMUX_REG_REG_PTEST  0x44
#define  G9_PINMUX_REG_REG_SD0_CD_X  0x48
#define  G9_PINMUX_REG_REG_SD0_PWR_EN  0x4c
#define  G9_PINMUX_REG_REG_FAN0  0x50
#define  G9_PINMUX_REG_REG_FAN1  0x54
#define  G9_PINMUX_REG_REG_SPI0_CS_X  0x58
#define  G9_PINMUX_REG_REG_SPI0_SDI  0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDO  0x60
#define  G9_PINMUX_REG_REG_SPI0_SCK  0x64
#define  G9_PINMUX_REG_REG_CAM_MCLK0_P_EN   0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK0_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PU_SEL   0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PIN_SEL_EN   0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK0_DRI_SEL   0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_MCLK0_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_MCLK0_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK0_SCT_EN   0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_MCLK0_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_MCLK0_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK0_OEX_EN   0x0
#define  G9_PINMUX_REG_REG_CAM_MCLK0_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_MCLK0_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_MCLK0_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK1_P_EN   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_MCLK1_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK1_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PU_SEL   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PIN_SEL_EN   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_MCLK1_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_DRI_SEL   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_MCLK1_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_MCLK1_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_SCT_EN   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_MCLK1_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_MCLK1_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK1_OEX_EN   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK1_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_MCLK1_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_MCLK1_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK2_P_EN   0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_MCLK2_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK2_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PU_SEL   0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PIN_SEL_EN   0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_MCLK2_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK2_DRI_SEL   0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_MCLK2_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK2_SCT_EN   0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_MCLK2_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_MCLK2_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK2_OEX_EN   0x8
#define  G9_PINMUX_REG_REG_CAM_MCLK2_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_MCLK2_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_MCLK2_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK3_P_EN   0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK3_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_MCLK3_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK3_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PU_SEL   0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PIN_SEL_EN   0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_MCLK3_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK3_DRI_SEL   0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK3_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_MCLK3_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_MCLK3_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK3_SCT_EN   0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK3_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_MCLK3_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_MCLK3_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK3_OEX_EN   0xc
#define  G9_PINMUX_REG_REG_CAM_MCLK3_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_MCLK3_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_MCLK3_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK4_P_EN   0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK4_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_MCLK4_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK4_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PU_SEL   0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PIN_SEL_EN   0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_MCLK4_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK4_DRI_SEL   0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK4_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_MCLK4_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_MCLK4_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK4_SCT_EN   0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK4_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_MCLK4_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_MCLK4_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK4_OEX_EN   0x10
#define  G9_PINMUX_REG_REG_CAM_MCLK4_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_MCLK4_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_MCLK4_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK5_P_EN   0x14
#define  G9_PINMUX_REG_REG_CAM_MCLK5_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_MCLK5_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK5_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PU_SEL   0x14
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PIN_SEL_EN   0x14
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_MCLK5_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK5_DRI_SEL   0x14
#define  G9_PINMUX_REG_REG_CAM_MCLK5_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_MCLK5_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_MCLK5_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_MCLK5_SCT_EN   0x14
#define  G9_PINMUX_REG_REG_CAM_MCLK5_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_MCLK5_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_MCLK5_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_MCLK5_OEX_EN   0x14
#define  G9_PINMUX_REG_REG_CAM_MCLK5_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_MCLK5_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_MCLK5_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR0_P_EN   0x18
#define  G9_PINMUX_REG_REG_CAM_XLR0_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_XLR0_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR0_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR0_PU_SEL   0x18
#define  G9_PINMUX_REG_REG_CAM_XLR0_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_XLR0_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_XLR0_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR0_PIN_SEL_EN   0x18
#define  G9_PINMUX_REG_REG_CAM_XLR0_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_XLR0_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_XLR0_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_XLR0_DRI_SEL   0x18
#define  G9_PINMUX_REG_REG_CAM_XLR0_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_XLR0_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_XLR0_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_XLR0_SCT_EN   0x18
#define  G9_PINMUX_REG_REG_CAM_XLR0_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_XLR0_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_XLR0_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR0_OEX_EN   0x18
#define  G9_PINMUX_REG_REG_CAM_XLR0_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_XLR0_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_XLR0_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR1_P_EN   0x1c
#define  G9_PINMUX_REG_REG_CAM_XLR1_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_CAM_XLR1_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR1_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR1_PU_SEL   0x1c
#define  G9_PINMUX_REG_REG_CAM_XLR1_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_CAM_XLR1_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_CAM_XLR1_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR1_PIN_SEL_EN   0x1c
#define  G9_PINMUX_REG_REG_CAM_XLR1_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_CAM_XLR1_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_CAM_XLR1_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_XLR1_DRI_SEL   0x1c
#define  G9_PINMUX_REG_REG_CAM_XLR1_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_CAM_XLR1_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_CAM_XLR1_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_CAM_XLR1_SCT_EN   0x1c
#define  G9_PINMUX_REG_REG_CAM_XLR1_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_CAM_XLR1_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_CAM_XLR1_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_CAM_XLR1_OEX_EN   0x1c
#define  G9_PINMUX_REG_REG_CAM_XLR1_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_CAM_XLR1_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_CAM_XLR1_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_P_EN   0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PU_SEL   0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PIN_SEL_EN   0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_DRI_SEL   0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_SCT_EN   0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_OEX_EN   0x20
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SDA_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_P_EN   0x24
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PU_SEL   0x24
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PIN_SEL_EN   0x24
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_DRI_SEL   0x24
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_SCT_EN   0x24
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_OEX_EN   0x24
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_PAD_HDMI_DDC_SCL_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PKG_TYPE_P_EN   0x28
#define  G9_PINMUX_REG_REG_PKG_TYPE_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PKG_TYPE_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PKG_TYPE_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PKG_TYPE_PU_SEL   0x28
#define  G9_PINMUX_REG_REG_PKG_TYPE_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PKG_TYPE_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PKG_TYPE_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PKG_TYPE_SCT_EN   0x28
#define  G9_PINMUX_REG_REG_PKG_TYPE_SCT_EN_OFFSET 10
#define  G9_PINMUX_REG_REG_PKG_TYPE_SCT_EN_MASK   0x400
#define  G9_PINMUX_REG_REG_PKG_TYPE_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPK_EN_P_EN   0x2c
#define  G9_PINMUX_REG_REG_SPK_EN_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SPK_EN_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SPK_EN_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPK_EN_PU_SEL   0x2c
#define  G9_PINMUX_REG_REG_SPK_EN_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SPK_EN_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SPK_EN_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SPK_EN_PIN_SEL_EN   0x2c
#define  G9_PINMUX_REG_REG_SPK_EN_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SPK_EN_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SPK_EN_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SPK_EN_DRI_SEL   0x2c
#define  G9_PINMUX_REG_REG_SPK_EN_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SPK_EN_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SPK_EN_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SPK_EN_SCT_EN   0x2c
#define  G9_PINMUX_REG_REG_SPK_EN_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SPK_EN_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SPK_EN_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPK_EN_OEX_EN   0x2c
#define  G9_PINMUX_REG_REG_SPK_EN_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SPK_EN_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SPK_EN_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_AUX0_P_EN   0x30
#define  G9_PINMUX_REG_REG_AUX0_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_AUX0_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_AUX0_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_AUX0_PU_SEL   0x30
#define  G9_PINMUX_REG_REG_AUX0_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_AUX0_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_AUX0_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_AUX0_PIN_SEL_EN   0x30
#define  G9_PINMUX_REG_REG_AUX0_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_AUX0_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_AUX0_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_AUX0_DRI_SEL   0x30
#define  G9_PINMUX_REG_REG_AUX0_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_AUX0_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_AUX0_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_AUX0_SCT_EN   0x30
#define  G9_PINMUX_REG_REG_AUX0_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_AUX0_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_AUX0_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_AUX0_OEX_EN   0x30
#define  G9_PINMUX_REG_REG_AUX0_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_AUX0_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_AUX0_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM0_P_EN   0x34
#define  G9_PINMUX_REG_REG_PWM0_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PWM0_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PWM0_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM0_PU_SEL   0x34
#define  G9_PINMUX_REG_REG_PWM0_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PWM0_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PWM0_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM0_PIN_SEL_EN   0x34
#define  G9_PINMUX_REG_REG_PWM0_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_PWM0_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_PWM0_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM0_DRI_SEL   0x34
#define  G9_PINMUX_REG_REG_PWM0_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_PWM0_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_PWM0_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM0_SCT_EN   0x34
#define  G9_PINMUX_REG_REG_PWM0_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_PWM0_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_PWM0_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM0_OEX_EN   0x34
#define  G9_PINMUX_REG_REG_PWM0_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_PWM0_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_PWM0_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM1_P_EN   0x38
#define  G9_PINMUX_REG_REG_PWM1_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PWM1_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PWM1_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM1_PU_SEL   0x38
#define  G9_PINMUX_REG_REG_PWM1_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PWM1_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PWM1_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM1_PIN_SEL_EN   0x38
#define  G9_PINMUX_REG_REG_PWM1_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_PWM1_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_PWM1_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM1_DRI_SEL   0x38
#define  G9_PINMUX_REG_REG_PWM1_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_PWM1_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_PWM1_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM1_SCT_EN   0x38
#define  G9_PINMUX_REG_REG_PWM1_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_PWM1_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_PWM1_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM1_OEX_EN   0x38
#define  G9_PINMUX_REG_REG_PWM1_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_PWM1_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_PWM1_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM2_P_EN   0x3c
#define  G9_PINMUX_REG_REG_PWM2_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PWM2_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PWM2_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM2_PU_SEL   0x3c
#define  G9_PINMUX_REG_REG_PWM2_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PWM2_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PWM2_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM2_PIN_SEL_EN   0x3c
#define  G9_PINMUX_REG_REG_PWM2_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_PWM2_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_PWM2_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM2_DRI_SEL   0x3c
#define  G9_PINMUX_REG_REG_PWM2_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_PWM2_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_PWM2_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM2_SCT_EN   0x3c
#define  G9_PINMUX_REG_REG_PWM2_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_PWM2_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_PWM2_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM2_OEX_EN   0x3c
#define  G9_PINMUX_REG_REG_PWM2_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_PWM2_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_PWM2_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM3_P_EN   0x40
#define  G9_PINMUX_REG_REG_PWM3_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PWM3_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PWM3_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM3_PU_SEL   0x40
#define  G9_PINMUX_REG_REG_PWM3_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PWM3_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PWM3_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM3_PIN_SEL_EN   0x40
#define  G9_PINMUX_REG_REG_PWM3_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_PWM3_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_PWM3_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM3_DRI_SEL   0x40
#define  G9_PINMUX_REG_REG_PWM3_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_PWM3_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_PWM3_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_PWM3_SCT_EN   0x40
#define  G9_PINMUX_REG_REG_PWM3_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_PWM3_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_PWM3_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PWM3_OEX_EN   0x40
#define  G9_PINMUX_REG_REG_PWM3_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_PWM3_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_PWM3_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PTEST_P_EN   0x44
#define  G9_PINMUX_REG_REG_PTEST_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_PTEST_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_PTEST_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_PTEST_PU_SEL   0x44
#define  G9_PINMUX_REG_REG_PTEST_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_PTEST_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_PTEST_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_PTEST_SCT_EN   0x44
#define  G9_PINMUX_REG_REG_PTEST_SCT_EN_OFFSET 10
#define  G9_PINMUX_REG_REG_PTEST_SCT_EN_MASK   0x400
#define  G9_PINMUX_REG_REG_PTEST_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_CD_X_P_EN   0x48
#define  G9_PINMUX_REG_REG_SD0_CD_X_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SD0_CD_X_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SD0_CD_X_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_CD_X_PU_SEL   0x48
#define  G9_PINMUX_REG_REG_SD0_CD_X_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SD0_CD_X_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SD0_CD_X_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_CD_X_PIN_SEL_EN   0x48
#define  G9_PINMUX_REG_REG_SD0_CD_X_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SD0_CD_X_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SD0_CD_X_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SD0_CD_X_DRI_SEL   0x48
#define  G9_PINMUX_REG_REG_SD0_CD_X_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SD0_CD_X_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SD0_CD_X_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SD0_CD_X_SCT_EN   0x48
#define  G9_PINMUX_REG_REG_SD0_CD_X_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SD0_CD_X_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SD0_CD_X_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_CD_X_OEX_EN   0x48
#define  G9_PINMUX_REG_REG_SD0_CD_X_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SD0_CD_X_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SD0_CD_X_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_P_EN   0x4c
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PU_SEL   0x4c
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PIN_SEL_EN   0x4c
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_DRI_SEL   0x4c
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_SCT_EN   0x4c
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_OEX_EN   0x4c
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SD0_PWR_EN_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN0_P_EN   0x50
#define  G9_PINMUX_REG_REG_FAN0_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_FAN0_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_FAN0_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN0_PU_SEL   0x50
#define  G9_PINMUX_REG_REG_FAN0_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_FAN0_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_FAN0_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN0_PIN_SEL_EN   0x50
#define  G9_PINMUX_REG_REG_FAN0_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_FAN0_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_FAN0_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_FAN0_DRI_SEL   0x50
#define  G9_PINMUX_REG_REG_FAN0_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_FAN0_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_FAN0_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_FAN0_SCT_EN   0x50
#define  G9_PINMUX_REG_REG_FAN0_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_FAN0_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_FAN0_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN0_OEX_EN   0x50
#define  G9_PINMUX_REG_REG_FAN0_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_FAN0_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_FAN0_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN1_P_EN   0x54
#define  G9_PINMUX_REG_REG_FAN1_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_FAN1_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_FAN1_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN1_PU_SEL   0x54
#define  G9_PINMUX_REG_REG_FAN1_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_FAN1_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_FAN1_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN1_PIN_SEL_EN   0x54
#define  G9_PINMUX_REG_REG_FAN1_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_FAN1_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_FAN1_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_FAN1_DRI_SEL   0x54
#define  G9_PINMUX_REG_REG_FAN1_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_FAN1_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_FAN1_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_FAN1_SCT_EN   0x54
#define  G9_PINMUX_REG_REG_FAN1_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_FAN1_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_FAN1_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_FAN1_OEX_EN   0x54
#define  G9_PINMUX_REG_REG_FAN1_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_FAN1_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_FAN1_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_CS_X_P_EN   0x58
#define  G9_PINMUX_REG_REG_SPI0_CS_X_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SPI0_CS_X_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SPI0_CS_X_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PU_SEL   0x58
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PIN_SEL_EN   0x58
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SPI0_CS_X_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_CS_X_DRI_SEL   0x58
#define  G9_PINMUX_REG_REG_SPI0_CS_X_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SPI0_CS_X_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SPI0_CS_X_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_CS_X_SCT_EN   0x58
#define  G9_PINMUX_REG_REG_SPI0_CS_X_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SPI0_CS_X_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SPI0_CS_X_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_CS_X_OEX_EN   0x58
#define  G9_PINMUX_REG_REG_SPI0_CS_X_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SPI0_CS_X_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SPI0_CS_X_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDI_P_EN   0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDI_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SPI0_SDI_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDI_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDI_PU_SEL   0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDI_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SPI0_SDI_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SPI0_SDI_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDI_PIN_SEL_EN   0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDI_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SPI0_SDI_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SPI0_SDI_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_SDI_DRI_SEL   0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDI_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SPI0_SDI_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SPI0_SDI_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_SDI_SCT_EN   0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDI_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SPI0_SDI_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SPI0_SDI_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDI_OEX_EN   0x5c
#define  G9_PINMUX_REG_REG_SPI0_SDI_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SPI0_SDI_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SPI0_SDI_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDO_P_EN   0x60
#define  G9_PINMUX_REG_REG_SPI0_SDO_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SPI0_SDO_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDO_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDO_PU_SEL   0x60
#define  G9_PINMUX_REG_REG_SPI0_SDO_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SPI0_SDO_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SPI0_SDO_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDO_PIN_SEL_EN   0x60
#define  G9_PINMUX_REG_REG_SPI0_SDO_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SPI0_SDO_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SPI0_SDO_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_SDO_DRI_SEL   0x60
#define  G9_PINMUX_REG_REG_SPI0_SDO_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SPI0_SDO_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SPI0_SDO_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_SDO_SCT_EN   0x60
#define  G9_PINMUX_REG_REG_SPI0_SDO_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SPI0_SDO_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SPI0_SDO_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SDO_OEX_EN   0x60
#define  G9_PINMUX_REG_REG_SPI0_SDO_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SPI0_SDO_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SPI0_SDO_OEX_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SCK_P_EN   0x64
#define  G9_PINMUX_REG_REG_SPI0_SCK_P_EN_OFFSET 0
#define  G9_PINMUX_REG_REG_SPI0_SCK_P_EN_MASK   0x1
#define  G9_PINMUX_REG_REG_SPI0_SCK_P_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SCK_PU_SEL   0x64
#define  G9_PINMUX_REG_REG_SPI0_SCK_PU_SEL_OFFSET 1
#define  G9_PINMUX_REG_REG_SPI0_SCK_PU_SEL_MASK   0x2
#define  G9_PINMUX_REG_REG_SPI0_SCK_PU_SEL_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SCK_PIN_SEL_EN   0x64
#define  G9_PINMUX_REG_REG_SPI0_SCK_PIN_SEL_EN_OFFSET 4
#define  G9_PINMUX_REG_REG_SPI0_SCK_PIN_SEL_EN_MASK   0xf0
#define  G9_PINMUX_REG_REG_SPI0_SCK_PIN_SEL_EN_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_SCK_DRI_SEL   0x64
#define  G9_PINMUX_REG_REG_SPI0_SCK_DRI_SEL_OFFSET 8
#define  G9_PINMUX_REG_REG_SPI0_SCK_DRI_SEL_MASK   0xf00
#define  G9_PINMUX_REG_REG_SPI0_SCK_DRI_SEL_BITS   0x4
#define  G9_PINMUX_REG_REG_SPI0_SCK_SCT_EN   0x64
#define  G9_PINMUX_REG_REG_SPI0_SCK_SCT_EN_OFFSET 12
#define  G9_PINMUX_REG_REG_SPI0_SCK_SCT_EN_MASK   0x1000
#define  G9_PINMUX_REG_REG_SPI0_SCK_SCT_EN_BITS   0x1
#define  G9_PINMUX_REG_REG_SPI0_SCK_OEX_EN   0x64
#define  G9_PINMUX_REG_REG_SPI0_SCK_OEX_EN_OFFSET 13
#define  G9_PINMUX_REG_REG_SPI0_SCK_OEX_EN_MASK   0x2000
#define  G9_PINMUX_REG_REG_SPI0_SCK_OEX_EN_BITS   0x1
